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<title cf:type="text"><![CDATA[Editorial department of the Journal of National University of Defense Technology -->新形态器件技术]]></title>
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<title xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="text"><![CDATA[Memristive neuromorphic computing approach combining calibration method and in-memory training]]></title>
<link><![CDATA[http://journal.nudt.edu.cn/gfkjdxxben/article/abstract/202305023]]></link>
<description xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="html"><![CDATA[Memristor based neuromorphic computing architecture has achieved good results in image classification, speech recognition and other fields, but when the memristor array has the problem of low yield, the performance declines significantly. A method combining memristive neuromorphic computing based calibration method with in-situ training was proposed, which increased the accuracy of multiplicative accumulation calculation by using the calibration method and reduced the training error by using the in-situ training method. In order to verify the performance of the proposed method, a multi-layer perceptron architecture was used for simulation. From the simulation results, the accuracy of the neural network is improved obviously (nearly 40%). Experimental results show that compared with the single calibration method, the precision of the network trained by the proposed method is improved by about 30%, and the precision of the network trained by the proposed method is improved by 0.29% when compared with other mainstream methods.]]></description>
<pubDate>2023/9/26 0:00:00</pubDate>
<category><![CDATA[新形态器件技术]]></category>
<author><![CDATA[DU Xiangyu, PENG Jie, LIU Haijun]]></author>
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<atom:name>DU Xiangyu, PENG Jie, LIU Haijun</atom:name>
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<title xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="text"><![CDATA[Accelerated fault injection algorithm for SRAM-based FPGA using whole frame upset]]></title>
<link><![CDATA[http://journal.nudt.edu.cn/gfkjdxxben/article/abstract/202305024]]></link>
<description xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="html"><![CDATA[UR-SB (unrecoverable-sensitive bits), which cannot be corrected by regular refresh, will cause long-term interruption of on-orbit service of satellite load. Thus, the impact of UR-SB needs to be evaluated and improved deeply by the fault injection tests. However, the proportion of UR-SB is extremely low. If the traditional bit-by-bit upset fault injection method is adopted, the fault injection tests would take too long time, and the efficiency is extremely low. A fault injection acceleration algorithm for static random access memory-based field programmable gate array based on whole frame upset was proposed, which can quickly filter out the configuration frames without UR-SB through whole frame upset fault injection. By taking dichotomy on the configuration frames with UR-SB, the precise positioning process of UR-SB can be speeded up effectively. Taking the commonly used XQR2V3000 device as an example, the simulation results indicate that the test efficiency can be improved by 207 times under the poor conditions, and the real data experimental results of the signal generation load by our group are increased by 949 times. These results demonstrate the validity of the acceleration algorithm proposed in this article.]]></description>
<pubDate>2023/9/26 0:00:00</pubDate>
<category><![CDATA[新形态器件技术]]></category>
<author><![CDATA[SUN Pengyue, LYU Shenglai, MAO Erkun, ZHANG Shuzheng, CHEN Lei, ZHOU Huan, HUANG Yangbo, LOU Shengqiang]]></author>
<atom:author xmlns:atom="http://www.w3.org/2005/Atom">
<atom:name>SUN Pengyue, LYU Shenglai, MAO Erkun, ZHANG Shuzheng, CHEN Lei, ZHOU Huan, HUANG Yangbo, LOU Shengqiang</atom:name>
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<title xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="text"><![CDATA[High-efficiency data loading and output buffering strategy for sparse convolutional computing]]></title>
<link><![CDATA[http://journal.nudt.edu.cn/gfkjdxxben/article/abstract/202305025]]></link>
<description xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="html"><![CDATA[In view of the problems such as inefficient data loading, insufficient utilization of multiply-accumulates resources, complex output buffering and addressing logic in existing neural network accelerators when processing sparse neural networks, a high-efficiency data loading and output buffering strategy for sparse convolutional computing was proposed. It performed an all-to-all multiply-accumulates operation on the non-zero input feature map data and the non-zero weights belonging to the same input channel, which reduces the difficulty of non-zero data pairing and improves the utilization of multiply-accumulates resources. By using input stationary calculation and intensive cyclic loading of input feature map data, it significantly reduced the number of data off-chip fetches. It optimized the output buffer design and solved the problems of address access contention and storage congestion during output buffering in existing solutions. Experimental results show that, when compare to fine-grained systolic accelerator with similar architectures, the process element area of the proposed architecture is decreased by 21.45%; the data loading speed is increased by 117.71% on average; the average utilization of multiplier is increased by 11.25%, reaching 89%.]]></description>
<pubDate>2023/9/26 0:00:00</pubDate>
<category><![CDATA[新形态器件技术]]></category>
<author><![CDATA[LIU Biao, CHEN Changlin, ZHANG Yufei, LIU Sitong, TANG Liqin, YU Hongqi]]></author>
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<atom:name>LIU Biao, CHEN Changlin, ZHANG Yufei, LIU Sitong, TANG Liqin, YU Hongqi</atom:name>
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<title xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="text"><![CDATA[Multi-memristor-array interconnection structure design for large scale CNN acceleration]]></title>
<link><![CDATA[http://journal.nudt.edu.cn/gfkjdxxben/article/abstract/202305026]]></link>
<description xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="html"><![CDATA[To address the problems of inefficient data loading and readout and poor flexibility of array collaboration in existing multi-memristor-array, a highly efficient and flexible multi-array interconnection architecture was proposed. The data loading strategy of the architecture supports data reuse in multiple weight mapping modes, reducing the need for off-chip data access; the readout network supports flexible combination of multiple processing units to achieve different scales of convolutional operations, as well as fast accumulation and readout of computation results, thus improving chip flexibility and overall computing power. Simulation experiments performed on the NeuroSim platform with running VGG-8 networks indicate a 146% increase in processing speed than that of the MAX<sup>2</sup> neural network accelerator, with only a 6% increase in area overhead.]]></description>
<pubDate>2023/9/26 0:00:00</pubDate>
<category><![CDATA[新形态器件技术]]></category>
<author><![CDATA[TANG Liqin, DIAO Jietao, CHEN Changlin, LUO Changhang, LIU Biao, LIU Sitong, ZHANG Yufei, WANG Qin]]></author>
<atom:author xmlns:atom="http://www.w3.org/2005/Atom">
<atom:name>TANG Liqin, DIAO Jietao, CHEN Changlin, LUO Changhang, LIU Biao, LIU Sitong, ZHANG Yufei, WANG Qin</atom:name>
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<title xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="text"><![CDATA[BRAM anti-irradiation design method for satellite payloads using time-sharing refreshing and location constraint]]></title>
<link><![CDATA[http://journal.nudt.edu.cn/gfkjdxxben/article/abstract/202305027]]></link>
<description xmlns:cf="http://www.microsoft.com/schemas/rss/core/2005" cf:type="html"><![CDATA[In order to solve the problem of lightweight and high-reliability anti-irradiation hardening for BRAM(block random access memory) in static random access memory-based field programmable gate array under the strict limitation of space-borne resources, BRAM anti-irradiation hardening design method based on time-sharing refreshing and location constraint was proposed. The time-sharing refreshing of the BRAM was realized through monitoring time slot of algorithm execution, and location constraint was added to effectively reduce the probability of simultaneous anomalies of two modules under the design of triple modular redundancy, effectively improving the reliability of BRAM radiation resistance with less resource consumption. The results of heavy ion acceleration test show that after adopting the time-sharing refreshing and location constraint hardening methods, the single event function interruption cross section of a certain type of satellite payload in our laboratory has decreased by about 81.63%. The BRAM anomaly on navigation satellites has been reduced from 3 stars, which occurred 3 times in 2 years, to 25 stars that have not occurred in 2 years, and the reliability of radiation resistance has been greatly improved.]]></description>
<pubDate>2023/9/26 0:00:00</pubDate>
<category><![CDATA[新形态器件技术]]></category>
<author><![CDATA[SUN Pengyue, LIU Xuhui, MAO Erkun, HUANG Yangbo, ZHANG Shuzheng, LOU Shengqiang]]></author>
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<atom:name>SUN Pengyue, LIU Xuhui, MAO Erkun, HUANG Yangbo, ZHANG Shuzheng, LOU Shengqiang</atom:name>
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