引用本文: | 欧钢,陈辉煌,沈振康.阵列排序器的VHDL设计方法[J].国防科技大学学报,1996,18(2):75-79.[点击复制] |
Ou Gang,Chen Huihuang,Shen Zhenkang.Sorter Array Processor Design by Using VHDL[J].Journal of National University of Defense Technology,1996,18(2):75-79[点击复制] |
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阵列排序器的VHDL设计方法 |
欧钢, 陈辉煌, 沈振康 |
(国防科技大学 电子技术系 湖南 长沙 410073)
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摘要: |
VHDL 是数字电路设计和描述的标准语言。讨论了脉动阵列结构的排序运算器及其改进电路,它们简洁的VHDL描述,经计算机的综合自动生成 FPGA 或 ASIC 的门级网表。实践证明,应用VHDL可以极大地提高设计效率。 |
关键词: 阵列处理,VHDL,电子设计自动化,现场可编程门阵列 |
DOI: |
投稿日期:1995-11-28 |
基金项目: |
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Sorter Array Processor Design by Using VHDL |
Ou Gang, Chen Huihuang, Shen Zhenkang |
(Department of Electronic Technology,NUDT,Changsha,410073)
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Abstract: |
VHDL is a standard language for the design and description of digital circuits. As a case study several array processors fullfilling the sort algorithm designed in VDHL are discussed here. Their concise VHDL description can be synthesized into FP-GA or ASIC gate-level netlist. Practice shows that applying VHDL can greatly improve the efficiency of digital system design. |
Keywords: array processor,VHDL,EDA,FPGA |
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