| 引用本文: | 郝建新,谢剑斌.用FPGA 实现先行进位单元阵列除法器.[J].国防科技大学学报,1997,19(1):66-70.[点击复制] |
| Hao Jianxin,Xie Jianbin.The Realization of Precedent Cellular Arrays Divider by Means of FPGA[J].Journal of National University of Defense Technology,1997,19(1):66-70[点击复制] |
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| 用FPGA 实现先行进位单元阵列除法器 |
| 郝建新, 谢剑斌 |
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(国防科技大学 电子技术系 湖南 长沙 410073)
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| 摘要: |
| 介绍了用FPGA 实现先行进位单元阵列除法器的原理及方法。本除法器在速度上不仅较软件方法快近十倍, 而且较传统的硬件除法器有很大的提高; 同时, 利用FPGA 设计技术, 将本除法器集成在一单片的FPGA 器件上, 从而为高速处理模块的实现提供了一条十分有效的途径。 |
| 关键词: FPGA, 单元阵列除法器 |
| DOI： |
| 投稿日期：1995-10-06 |
| 基金项目: |
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| The Realization of Precedent Cellular Arrays Divider by Means of FPGA |
| Hao Jianxin, Xie Jianbin |
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(Department of Electronic Technology, NUDT, Changsha, 410073)
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| Abstract: |
| The theory and method of precedent cellular arrays divider by means of FPGA are introduced. The divider is not only almost ten times faster than the software method, but also faster than the hardware divider; at the same time, the divider is integrated into one chip by means of FPGA technology. This provides a very effect access to realizing the high-speed processing module. |
| Keywords: FPGA, cellular arrays divider |
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