| 引用本文: | 曾芷德.特大规模组合电路高速测试生成系统ATGTA-1.[J].国防科技大学学报,1999,21(2):37-41.[点击复制] |
| Zeng Zhide.The High Speed Test Generation System ATGTA-1 for Very Large Scale Combination Circuit[J].Journal of National University of Defense Technology,1999,21(2):37-41[点击复制] |
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| 特大规模组合电路高速测试生成系统ATGTA-1 |
| 曾芷德 |
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(国防科技大学 计算机系 湖南 长沙 410073)
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| 摘要: |
| 针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法, 并建成了相应的测试生成系统ATGTA-1。该系统采用有限回溯测试模式产生方法生成测试码, 采用n (机器字长) 个测试码并行的单故障传播方法模拟验证测试覆盖。测试生成与故障模拟为n对1紧耦合集成方式。该系统运行10个Benchmark电路, 取得了低测试长度、高故障覆盖、高效率的良好效果。 |
| 关键词: 全扫描设计, 有限回溯测试模式产生, n 对1紧耦合集成方式, 测试码并行, 单故障传播, 特大规模组合电路 |
| DOI： |
| 投稿日期：1998-06-30 |
| 基金项目:国家自然科学基金资助项目 |
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| The High Speed Test Generation System ATGTA-1 for Very Large Scale Combination Circuit |
| Zeng Zhide |
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(Department of Computer, NUDT, Changsha, 410073)
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| Abstract: |
| This paper presents a high speed test generation method specifically for very large scale combination circuit and full scan-designed circuit. This method is used together with the finite backtracing test pattern generation method to generate test code, and then simulates to validate the fault covering by means of single fault propogating method with n (machine word) test code parallelised. The mode for test generation and fault simulation is n to 1 tight coupled integrating mode. With testing the method with 10 benchmark circuits, the result is good for low test pattern length, high fault coverage and high efficiency. |
| Keywords: full scan-design, finite backtracing test pattern generation, n to 1 tight coupled integrating mode, test code parallelism, single fault propogation, very large scale combination circuit |
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