| 引用本文: | 江明明,吴美平,庹洲慧.捷联惯导系统异步锁存计数器设计.[J].国防科技大学学报,2003,25(2):95-98.[点击复制] |
| JIANG Mingming,WU Meiping,TUO Zhouhui.Design for Asynchronism Latching Accumulator of SINS[J].Journal of National University of Defense Technology,2003,25(2):95-98[点击复制] |
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| 捷联惯导系统异步锁存计数器设计 |
| 江明明, 吴美平, 庹洲慧 |
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(国防科技大学 机电工程与自动化学院，湖南 长沙 410073)
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| 摘要: |
| 介绍了采用FPGA芯片实现揭联惯导系统异步锁存计数器的设计方法，对计数器的性能进行了分析、测试。 |
| 关键词: 锁存计数器 惯导系统 FPGA |
| DOI： |
| 投稿日期：2003-09-27 |
| 基金项目: |
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| Design for Asynchronism Latching Accumulator of SINS |
| JIANG Mingming, WU Meiping, TUO Zhouhui |
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(College of Mechatronics Engineering and Automation,National Univ. of Defense Technology，Changsha 410073，China)
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| Abstract: |
| The method which adopts FPGA chip to design for asynchronism latching accumulator of SINS is introduced. The accumulator's performance is analyzed and tested. |
| Keywords: latching accumulator inertial navigation system FPGA |
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