| 引用本文: | 陈胜刚,付兴飞,曾思,等.用于DDR3访存优化的数据缓冲机制.[J].国防科技大学学报,2017,39(6):39-44.[点击复制] |
| CHEN Shenggang,FU Xingfei,ZENG Si,et al.DDR3 data buffering for memory access optimization[J].Journal of National University of Defense Technology,2017,39(6):39-44[点击复制] |
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| 用于DDR3访存优化的数据缓冲机制 |
| 陈胜刚1,2, 付兴飞1, 曾思1, 刘胜1 |
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(1. 国防科技大学 计算机学院， 湖南 长沙 410073;2. 并行与分布处理国家重点实验室， 湖南 长沙 410073)
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| 摘要: |
| 为提高DDR3控制器访存效率，设计了基于DDR3存储器预取访问数据长度的数据缓冲机制，将访存请求分为三种基本类型并分别排队处理，降低数据丢弃和实际动态随机访问存储器访问发生次数。针对图像和视频类应用程序的实验结果表明，相对于传统先到先服务的DDR3访存控制器，该机制取得了平均21.3%、最好51.3%的性能提升，硬件开销在可接受范围内。 |
| 关键词: DDR3控制器 访存优化 数据缓冲 |
| DOI：10.11887/j.cn.201706007 |
| 投稿日期：2016-07-20 |
| 基金项目:国家自然科学基金资助项目（61402499，61602493，61402500，61672526） |
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| DDR3 data buffering for memory access optimization |
| CHEN Shenggang1,2, FU Xingfei1, ZENG Si1, LIU Sheng1 |
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(1. College of Computer, National University of Defense Technology, Changsha 410073, China;2.
2. National Laboratory for Parallel and Distributed Processing, Changsha 410073, China)
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| Abstract: |
| In order to improve the memory access efficiency of the DDR3 memory controller, a data buffering mechanism based on DDR3 memory access burst length was proposed. The application requests were guided into three different queues. The data buffering mechanism can make use of the additional data obtained from DRAM(dynamic random access memory) in one of the former request, thus reducing the actual external DRAM access needed. Experiments on several image and video application show that the proposed mechanism can improve the memory controller by an average 21.3% and a peak by 51.3% at an acceptable hardware cost when compared with the FCFS (first-come-first-serve) baseline DDR3 memory controller. |
| Keywords: DDR3 memory controller memory access optimization data buffering |
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