Design for Asynchronism Latching Accumulator of SINS
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摘要:
介绍了采用FPGA芯片实现揭联惯导系统异步锁存计数器的设计方法,对计数器的性能进行了分析、测试。
Abstract:
The method which adopts FPGA chip to design for asynchronism latching accumulator of SINS is introduced. The accumulator's performance is analyzed and tested.
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江明明,吴美平,庹洲慧.捷联惯导系统异步锁存计数器设计[J].国防科技大学学报,2003,25(2):95-98. JIANG Mingming, WU Meiping, TUO Zhouhui. Design for Asynchronism Latching Accumulator of SINS[J]. Journal of National University of Defense Technology,2003,25(2):95-98.