The design extraction from HDL description has been greatly needed in modern VLSI design process,such as the design verification，low power analysis，test generation and so on.This paper presents a new circuit extraction method using program slicing technique,and develops an elegant theoretical basis, based on program slicing, for circuit extraction from Verilog description. With the technique we can obtain a “chaining slice” for each given signal of interest.Our method has advantage in its fine grain,without writing-style limitation and in dealing with more Verilog components characteristics.The technique has been used in the design process and the results show its convenience，efficiency and good practicability.