The virtual memory is a staple in modern processor system. In virtual addressing scheme, the translation from virtual address to physical address is one of the highest frequency core service in the pipe line, and tends to be on the critical path determining the clock cycle of the processor. In order to speed up the address translation, the most modern processors have designed a hardware unit called translation look-aside buffer(TLB). Based on analyzing the traditional address mapping mechanism of TLB, this paper has put forward the regions and Cache line tag pre-validation to optimize the translation, and removed the TLB delay bottleneck in the whole memory access.