A structure of TLB for low power is introduced. The idea of the proposed TLB is based on the spatial locality, which is the result of combining with the block buffering technology and adjustment of the CAM structure. All of these make the TLB for low power. With Simple Scalar 3.0, a simulation of the proposed TLB and some traditional TLB structures were made to observe the miss ratio. The simulation results from the modified CACTI3 show that the proposed TLB structure can reduce power*delay about 85%, 80%, 66%, and 66%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a bank-TLB. Therefore the proposed TLB can achieve low power.