Due to technology scaling, radiation-induced soft error has been increasing in VLSI systems. Designers have to consider the problem of reliability caused by soft errors. Selective hardening of vulnerable nodes in circuits using resilient registers is a prevalent solution, which can effectively reduce soft error rate of logic circuits. This paper gives a summary of some soft error immune registers, and then provides quantitative analysis and comparison in reliability of eight kinds of registers. The result concludes that temporal spatial dual modular redundancy structure shows better reliability. The existent reliable registers brings about great overhead that cannot be avoided, so this paper designs a timing shift-based Dynamic Master Temporal Spatial - Dual modular redundancy Register (DMTS-DR). The experiment results show that the proposed register is not only able to immunize SEUs in itself, but can also mask SETs propagated from combinational logic efficiently. Compared to other reliable registers, area overhead and delay penalty of DMTS-DR have been reduced greatly. DMTS-DR has better tradeoff among reliability, area and speed.