YHFT-DX is a high performance DSP designed by national university of defense technology. This paper focuses on improving Cache performance, investigates optimization methods to reduce Cache miss stall penalties, designs and implements an optimization method focusing on one level data Cache controller in high frequency and high performance DSP-miss pipelining. Compared with traditional optimization methods, this method can deal with continual cache misses in pipeline, which overlaps multi Cache miss stalls, and then it can achieve the goal of reducing Cache miss stall penalties. Applying the method to the design and optimization in one level data Cache controller in YHFT-DX DSP, the Cache miss stall is reduced from 8 cycles to 2 cycles, and the system performance is evidently improved.