Dynamic and differential logic styles are proposed as a typical differential power analysis (DPA) resistant technology. Because of the constant transition rate of dynamic and differential logic gates, the correlation between power consumption and signal values is significantly reduced. In this paper, a novel look-up-table (LUT) based differential logic (LBDL) and the design method based on this logic are presented. Instead of a full custom design, this method combines some modification with a regular standard cell design flow. Thus, have a better practicability. Unlike WDDL (Wave Dynamic Differential Logic), which can also be implemented by standard cell design flow, the transition time of LBDL gates is independent of input values, hence power consumption of LBDL is more constant. Experimental results indicate that the LBDL-based design method can eliminates most of the power leakage.