For the drawbacks existent in single-thread fetch pipeline to improve the efficiency, a high-performance fetch pipeline structure is proposed in this paper based on the platform of the VLIW digital signal processor (DSP). It can support the detection and void for the invalid fetch, bypass for the missing fetch, which reduces the unnecessary cache access and fetch pipeline stall. The structure also inducts dedicated hardware which supports the software pipeline of scheduled compilation to improve the parallelism of instruction. It reduces the code memory space, and the idle cycles of released single-threaded pipeline is reached up to about 46.34%. Compared with the fetch pipeline before optimized, experiment results show that the code storage space is reduced about 11.93%, the average execution cycle is shortened about 8.67%, the cache access times is decreased about 12.84%, the suspension period of instruction cache is shortened about 7.86%, and the single-threaded instruction throughput of processor is increased by 11.7%.