DICE cell is an effective method to mitigate SEU effects. SEU, however, still occur in DICE cell-based SRAMs, due to the weakness of DICE cell during reading and writing, and the weakness in the peripheral circuits. A separated-bit-line structure is proposed to handle the DICE cell’s upset during reading and writing, and a double module redundancy method is presented to resolve the upset in the peripheral circuits. The simulation results show these methods are effective to mitigate SEU from DICE cell based SRAMs.