Buffer resources are key components of the on-chip router, and their structures exert significant influence on the performance and power consumption of the interconnection network. In general, asynchronous FIFO based on shift registers is adopted to implement on-chip buffer resources. Packets transmitted traverse the FIFO queue step by step, leading to higher propagation delay of packets and larger transition counts in the circuit. In this research, an asynchronous FIFO based on hierarchical bit-line buffer is proposed, and then a new asynchronous on-chip router is presented in detail. Compared with the traditional asynchronous router, the newly presented one has lower hardware complexity and power consumption. Experiments show that the new router can achieve 39.3% area saving and 41.1% power reduction when the depth of asynchronous FIFO is configured with 8.