Targeting at the mapping of key loops onto CGRA (Coarse-Grained Reconfigurable Architectures), this research proposes a novel approach called memory-aware kernel loop pipelining mapping (MALP). The RCP_CGRA model and the critical loop mapping formulation were shown first. Based on polyhedral model, then the array clustering and data domain partition were presented. An analysis of the critical loop storage requirement was described. Based on this analysis result, the MALP provided an efficient way for loop mapping under the resource constraints of CGRA. Experiment results show that MALP can improve the data throughput rate while costing less resource. MALP makes the loop mapping on CGRA more efficient.