With the growing complexity of VLSI designs, functional verification and debugging has become a resource-intensive bottleneck in modern CAD flows, consuming as much as 60% of the total design cycle. Error localization in circuits is difficult and time-consuming. Therefore an efficient error debugging and localization method is necessary for hardware design. Recently there are many different contributions to research on error localization in circuits. Firstly, the categories and workflow of error debugging method were introduced. The fundamental principles of SAT-based error localization method were described. Then the existing algorithms were introduced and analyzed. Furthermore, the research results about extract unsatisfiable subformulae, which can strongly improve the efficiency and accuracy of error localization, were presented. Finally, the current challenges were discussed, and the future research directions of error localization in circuits were outlined.