A bi-directional non-blocking ring architecture was proposed for the multicore processor with relative less amount of high-performance cores. The architecture consists of five ring layers of three different types for commands, huge data and small data transportation, respectively. The source routing strategy was employed and an equipment state control interconnection was designed for congestion management. The router has a bufferless and contention-free structure and each hop only takes one clock cycle, thus minimizing the transmission delay and realizing deterministic routing. Considering the long links and high bandwidth of the ring, experiments were carried out to find a proper repeater insertion method, and the crosstalk optimizing methods, such as inverter insertion crosswise between two neighborhood lines and arranging neighborhood lines in signal transport direction, were studied to conduct physical design for the ring and delay optimization for the long links. Implementation results show that the designed ring′s bandwidth is 256 GByte/s @1 GHz, which can fulfill the data communication demands of the digital signal processing applications.