This paper presents a high speed test generation method specifically for very large scale combination circuit and full scan-designed circuit. This method is used together with the finite backtracing test pattern generation method to generate test code, and then simulates to validate the fault covering by means of single fault propogating method with n (machine word) test code parallelised. The mode for test generation and fault simulation is n to 1 tight coupled integrating mode. With testing the method with 10 benchmark circuits, the result is good for low test pattern length, high fault coverage and high efficiency.