Parallel Pipeline Forwarding Engine Design andPerformance Evaluation
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    Abstract:

    With the rapid development of communication technology, optical transmit technique demands higher requirement of the core router's forwarding performance. OC192 POS interfaces have made the core router's forwarding engine a new bottleneck. Further development of optical transmit technique has exceeded the maximum accessing ability of DRAM, which makes impossible the design of new forwarding engine with one chip of DRAM. New hardware parallel forwarding engine design is offered on the basis of Gupat's DIR 24 8 BASIC forwarding architecture, taking advantage of the parallel of multiplex DRAM chips. In order to get really performance of the parallel forwarding engine design, IP packet header trace and routing table's dump of Internet core router node are used as the input of the target system's simulator. The result shows that the parallel forwarding engine can achieve linear speedup with the increase of parallel basic forwarding tables.

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History
  • Received:October 20,2004
  • Revised:
  • Adopted:
  • Online: March 25,2013
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