An efficient VLSI architecture for two-dimension DWT is proposed and illustrated in detail for the CDF9/7 wavelet transform. The improved lifting scheme is adopted to reduce the critical path delay. Coefficients of the multipliers are transformed into CSD forms and then the multiplications are substituted by shift-add operations. The row transform and column transform are running simultaneously and pipeline design is used to optimize the architecture. This architecture is implemented through behavioral VHDL. The results are identical with those of the software simulation, and thus the validity of this architecture is proved. Compared with other architectures, this one has the advantages of faster computation time and almost 100% hardware utilization.