This paper proposes a Wallace-tree based new DCT/IDCT architecture, which does not depend on ROM and multipliers any more, but utilizes low cost adders, shifts and 4-2 compressors to implement the multiplication-dense DCT/IDCT algorithm. Designed and synthesized by SMIC 0.18 μm technology, the architecture could achieve 100Mpixels/sec throughout with cost of only36 141transistors and 1024 bits transform memory. As a result, a far better performance of time series and space is obtained than that of the existing architecture.