Various sub-pixel interpolation technologies are adopted in video coding applications. A multi-standard configuration interpolation architecture is proposed. It consists of two independent 8-tap filters. It can also reduce about 46% interpolation computation by a two-step filter method. Each filter includes a filter parameter register, which stores different filter parameter for various video standards. As a pipeline architecture, filter can have three filter results in one cycle. In SMIC 0.13μm CMOS process, the frequency of this architecture is up to 400MHz, and the area is about 32.6k gates. The experiment results show that, working on 250MHz, this architecture can satisfy the interpolation computation requirements of encoding 1920×1080,30fps HD video sequences.