Design and Performance Analysis of an InterconnectInterface for Multi-Core Microprocessor
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    Abstract:

    Parallelism is the most important way to improve the performance of computer. With the development of the integrated circuits' manufacture process, besides integrating more processor cores into one processor chip, building multi-way parallelism system through high-speed interconnect interface is the main method to increase the parallelism of high-performance computer. A design scheme of an interconnect interface for multi-core microprocessor was proposed. The proposed interface was based on a simplified PCI Express bus protocol and adopted the technology of high-speed serial data transferring. Cache coherence packet and large block data transfer packet were all supported. The interface can be used for connecting four processor nodes directly. Simulation results show that the max valid bandwidth per interface can reach 64Gbps and the minimum transfer delay is 120ns. The balance of the bandwidth and the transfer delay is reached, meeting the requirement of transferring different type of packets.

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History
  • Received:October 09,2009
  • Revised:
  • Adopted:
  • Online: September 06,2012
  • Published:
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