The power leakage covers more and more of the consumption of power, especially when the production of highly integrated circuit has reached the level of very deep submicron, thus it becomes the main source of the power leakage of the microprocessor. Power leakage is closely related to voltage, leakage current and the amount of transistors. Cache is the sizable fraction of the total microprocessor, and its leakage power optimization must be firstly considered in low power microprocessor design. Besides process improvement, the leakage power of caches can be adaptively reduced by monitoring and controlling its operating states at architectural level. In light of this idea, a dynamic resizing policy based on cache replacement algorithm was proposed. The cache was dynamically resized on-so-called logical way granularity according to cache operating states. Simulation results show that dynamic resizing policy can reduce cache leakage power by 76.6% without obviously performance drop, especially for high associative caches.