As technology feature scales down, SER (Soft Error Rates) induced in the combinational logic wins increasing attention. A mixed-mode simulation method is proposed for computing SER in combinational logic, which is aimed at solving the slow HSPICE simulation speed and the low precise of traditional methods in treating re-convergence. A Mixed-Mode Analysis Tool for Combinational Logic based on this method was implemented. Re-convergence logic gates were simulated with HSPICE; a fast pulse propagate algorithm was used to simulate others. The simulation results illustrate that the proposed method gains a close precision to HSPICE with a faster speed. Compared with the prevalent SER analysis method, it is found that our proposed method can factually reflect the SER in combinational circuits where there are many re-convergence logic gates.