A clock error calibration algorithm based on phase lock loop in GNSS time synchronization receiver
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    Abstract:

    GNSS receiver synchronizes local clock by calibrating clock error obtained from GNSS satellite signal. A novel local clock error calibration algorithm is developed. The time synchronization procedure was considered as a PLL model. In this model, phase detector was achieved by PVT solution, VCO was achieved by local clock adjusting interface, and the PLL lock the phase of local clock and GNSS clock. The total PLL time synchronization loop errors were analyzed, the relationship of each error item and parameters of PLL was analyzed, and the best PLL design criteria were developed. Finally, the time synchronization algorithm was tested on a COMPASS navigation receiver.

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History
  • Received:June 07,2012
  • Revised:
  • Adopted:
  • Online: May 21,2013
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