In order to improve the memory access efficiency of the DDR3 memory controller, a data buffering mechanism based on DDR3 memory access burst length was proposed. The application requests were guided into three different queues. The data buffering mechanism can make use of the additional data obtained from DRAM(dynamic random access memory) in one of the former request, thus reducing the actual external DRAM access needed. Experiments on several image and video application show that the proposed mechanism can improve the memory controller by an average 21.3% and a peak by 51.3% at an acceptable hardware cost when compared with the FCFS (first-come-first-serve) baseline DDR3 memory controller.