To cope with the timing problem of placement in the very large integrated circuit, a timing-driven optimization method for placement was proposed. Firstly, the design was analyzed by a timing evaluation tool and the timing violation paths were collected. A rough placement method was used on the moved cells between any two successive fixed cells in those paths to smooth the nets. After that, a detailed placement based on quadratic timing model was used to optimize the timing characteristics. For the given benchmarks and the evaluation method in ICCAD 2015 contest, the experimental results show that both the worst negative slack and the total negative slack are improved, and the overall timing performance is improved by 45~350 min.