An FPGA(field-programmable gate array) verification platform for memory link interface of manycore processor was proposed to test the function and reliability of the main components of the processor′s memory access link. Three key technologies, the on-chip read-write requests automatic generation and result checking mechanism, the hardware UDP(user datagram protocol) protocol stack in Ethernet interface and the multi-lane parallel link between FPGA chips were proposed and implemented. Experiments on the platform show that the proposed technologies are correct, they not only enrich the ways of the random request generation and result checking for functional verification, but also can test and evaluate the logics of link errors detection and lanetolane deskew. The proposed platform has been used to verify a real many-core processor in which the function of memory link interface is correct, so the validity of the verification is proved.