In some low precision applications, pipelined floating-point reciprocal operation is required actually. Based on SRT-4 algorithm, a pipelined floating-point reciprocal operation unit was designed and implemented, which is constructed as a 6-stage pipeline unit, resulting in an 8-bit valid fractions. In order to support hardware process of denormal numbers, the unit was improved to get higher performance, which is constructed as a 8-stage pipeline unit, adding source operand pre-normalization and result post-normalization function components and supporting hardware process of denormal numbers. After logic synthesis, the area of the unit was increased by 19.23%, which is reasonable. The timing of the unit was not affected obviously and met the expected frequency goal of 1.6 GHz.