存储体编译和布局协同的片上缓存设计方法
2024,46(1):198-203
刘必慰
国防科技大学 计算机学院, 湖南 长沙 410073，liubiwei04@nudt.edu.cn
熊琪
国防科技大学 理学院, 湖南 长沙 410073
杨茗
国防科技大学 军政基础教育学院, 湖南 长沙 410073
宋雨露
国防科技大学 军政基础教育学院, 湖南 长沙 410073
国防科技大学 计算机学院, 湖南 长沙 410073，liubiwei04@nudt.edu.cn
熊琪
国防科技大学 理学院, 湖南 长沙 410073
杨茗
国防科技大学 军政基础教育学院, 湖南 长沙 410073
宋雨露
国防科技大学 军政基础教育学院, 湖南 长沙 410073
摘要：
为了提高片上缓存的速度、降低面积和功耗,提出了一种存储体编译和布局协同的片上缓存设计方法。该方法基于存储体在芯片上的不同空间位置预估该存储体的时序余量,分别采用拆分/合并、尺寸调整、阈值替换和长宽比变形等多种配置参数穷举组合进行存储体编译,根据时序余量选择最优的静态随机存取存储器存储体编译配置。将该方法与现有的物理设计步骤集成为一个完整的设计流程。实验结果表明,该方法能够降低约9.9%的功耗,同时缩短7.5%的关键路径延时。
为了提高片上缓存的速度、降低面积和功耗,提出了一种存储体编译和布局协同的片上缓存设计方法。该方法基于存储体在芯片上的不同空间位置预估该存储体的时序余量,分别采用拆分/合并、尺寸调整、阈值替换和长宽比变形等多种配置参数穷举组合进行存储体编译,根据时序余量选择最优的静态随机存取存储器存储体编译配置。将该方法与现有的物理设计步骤集成为一个完整的设计流程。实验结果表明,该方法能够降低约9.9%的功耗,同时缩短7.5%的关键路径延时。
基金项目：
国家部委基金资助项目 第一作者:刘必慰
国家部委基金资助项目 第一作者:刘必慰
On-chip cache design method for cooperative memory compilation and layout
LIU Biwei
College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China,liubiwei04@nudt.edu.cn
XIONG Qi
College of Sciences, National University of Defense Technology, Changsha 410073, China
YANG Ming
College of Basic Education, National University of Defense Technology, Changsha 410073, China
SONG Yulu
College of Basic Education, National University of Defense Technology, Changsha 410073, China
College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China,liubiwei04@nudt.edu.cn
XIONG Qi
College of Sciences, National University of Defense Technology, Changsha 410073, China
YANG Ming
College of Basic Education, National University of Defense Technology, Changsha 410073, China
SONG Yulu
College of Basic Education, National University of Defense Technology, Changsha 410073, China
Abstract：
In order to improve the speed of on-chip cache and reduce the area and power consumption, an on-chip cache design method based on cooperative memory compilation and layout was proposed. This method estimated the timing margin of memory array based on its different spatial positions on chip, and then performed memory compilation through exhaustive combination of various configuration parameters such as splitting/ merging, size adjustment, threshold replacement and aspect ratio deformation. The best static random-access memory compilation configuration was selected according to the timing margin. This method was integrated with the existing physical design steps into a complete design flow. Experimental results show that this method can reduce the power consumption by about 9.9% and the critical path delay by 7.5%.
In order to improve the speed of on-chip cache and reduce the area and power consumption, an on-chip cache design method based on cooperative memory compilation and layout was proposed. This method estimated the timing margin of memory array based on its different spatial positions on chip, and then performed memory compilation through exhaustive combination of various configuration parameters such as splitting/ merging, size adjustment, threshold replacement and aspect ratio deformation. The best static random-access memory compilation configuration was selected according to the timing margin. This method was integrated with the existing physical design steps into a complete design flow. Experimental results show that this method can reduce the power consumption by about 9.9% and the critical path delay by 7.5%.
收稿日期：
2021-11-01
2021-11-01
