Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism (ILP) by VLIW. Research of the VLIW compiler for distributed register file has been a hotspot. KernelC compiler ISCD developed by Stanford University was the first of its kind to deal with VLIW schedule for distributed register file and the only compiler actually applied as well. However, it limited the program for its weakness of scheduling the code with heavy workload. Based on ISCD, this paper presents a new VLIW schedule strategy. Experimental results show that it can deal with distributed register file allocation with heavy workload very well.