The key factors that affect Single Event Latch-up sensitivity were investigated. In view of 180nm bulk technology, based on calibrated CMOS inverter model, TCAD method was adopted to study the effects of particle incident position, temperature, and well / substrate contact position, NMOS and PMOS spacing and other factors on SEL sensitivity. Simulation and analysis shows that, SEL response varies greatly at different nodes, and the study identified the sensitive nodes of the CMOS inverter of SEL occurrence, and explored the relationship between temperature, well / substrate contact position, NMOS and PMOS drain distance and LET threshold when SEL occurred, then analyzed theoretically and summarized the reinforcement for reducing SEL sensitivity. The results can provide effective guidance to the anti-SEL design.