With the continuous advancement of advanced processes and technologies, in order to ensure the accuracy of data during high-speed transmission, equalizers need to provide higher compensation and lower power consumption to achieve efficient communication. A high-gain and low-power adaptive CTLE(continuous time linear equalizer) was designed based on the 12 nm CMOS(complementary metal-oxide-semiconductor) process, which adopted a two-stage cascade structure to compensate for channel attenuation and improve the quality of the received signal. In addition, the adaptive module used the Sign-sign Least Mean Square algorithm to accelerate the convergence speed of the tap coefficients. Simulation results showed that when the transmission rate was 16 Gbps, the equalizer could compensate for a half-bit rate channel attenuation of -15.53 dB, and the equalizer coefficients converged within 16×10^4 UI data. Moreover, after convergence, the received error rate was lower than 10^-12.