The rapid development of high-performance computing (HPC) and artificial intelligence (AI) demands networks with higher bandwidth, larger scale, and greater cost. As the core of interconnection networks, topology design is constrained by multiple factors, including the number of ports per router chip, the number of virtual channels, and packaging density. This study reviews approximately thirty topologies proposed by academia and industry, providing detailed analysis of the most representative and recent designs. It examines the design challenges of adaptive routing in high-radix networks, compares the performance and cost of multiple topologies, and provides recommendations for topology selection. Finally, the paper identifies key challenges in topology design and outlines future trends, including application-driven, cost-effective network topologies; power-supply-constrained designs that align with facility power capacity; the unification of intra-node network protocols; and the continual expansion of supernode scale. Future topologies are expected to integrate intra-node and inter-node designs in a coordinated manner.