| 引用本文: | 苏金树,金士尧.高性能多处理机系统总线设计技术.[J].国防科技大学学报,1994,16(3):54-57.[点击复制] |
| Su Jinshu,Jin Shiyao.Design Technology of High Performance Bus for Multi-Processor[J].Journal of National University of Defense Technology,1994,16(3):54-57[点击复制] |
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| 高性能多处理机系统总线设计技术 |
| 苏金树, 金士尧 |
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(国防科技大学 计算机系 湖南 长沙 410073)
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| 摘要: |
| 本文以银河仿真Ⅱ型计算机为背景，论述面向多处理机的高性能总线的体系结构、总线特点、总线数据传输、多处理机通信等总线设计技术。 |
| 关键词: 仿真机 多处理机系统 总线设计 |
| DOI： |
| 投稿日期：1993-12-18 |
| 基金项目: |
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| Design Technology of High Performance Bus for Multi-Processor |
| Su Jinshu, Jin Shiyao |
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(Department of Computer Science)
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| Abstract: |
| Based on YH-F2 simulation computer, the paper describes some aspects of bus design technology, such as the architecture of high performance bus，bus features，data transfermation on bus and protocol of multi-processor communication. |
| Keywords: simulation computer,multi-processor system,bus design |
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