| 引用本文: | 陈海燕,邓让钰,邢座程.高性能微处理器TLB的优化设计.[J].国防科技大学学报,2004,26(4):10-14.[点击复制] |
| CHEN Haiyan,DENG Rangyu,XING Zuocheng.The Optimization Design of TLB of High Performance Processor[J].Journal of National University of Defense Technology,2004,26(4):10-14[点击复制] |
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| 高性能微处理器TLB的优化设计 |
| 陈海燕, 邓让钰, 邢座程 |
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(国防科技大学 计算机学院，湖南 长沙 410073)
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| 摘要: |
| 虚拟存储是现代微处理器系统必不可少的存储模式。在虚存模式下，虚拟地址到物理地址的变换是流水线中最频繁的核心服务，容易处于决定处理器时钟周期的关键路径上。为加快虚存的访问，现代高性能微处理器实现了一种硬件地址映射结构：转换后援缓冲器(简称TLB)；在分析TLB传统的地址映射机制的基础上，提出了基于虚区域和Cache块标记的预验证技术，结果表明该技术优化了TLB的设计,避免了TLB访问时延成为访存的瓶颈。 |
| 关键词: 虚拟存储 TLB 地址变换 预验证 Cache块标记 |
| DOI： |
| 投稿日期：2004-03-10 |
| 基金项目:国家自然科学基金资助项目(90207011) |
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| The Optimization Design of TLB of High Performance Processor |
| CHEN Haiyan, DENG Rangyu, XING Zuocheng |
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(College of Computer，National Univ. of Defense Technology, Changsha 410073,China)
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| Abstract: |
| The virtual memory is a staple in modern processor system. In virtual addressing scheme, the translation from virtual address to physical address is one of the highest frequency core service in the pipe line, and tends to be on the critical path determining the clock cycle of the processor. In order to speed up the address translation, the most modern processors have designed a hardware unit called translation look-aside buffer(TLB). Based on analyzing the traditional address mapping mechanism of TLB, this paper has put forward the regions and Cache line tag pre-validation to optimize the translation, and removed the TLB delay bottleneck in the whole memory access. |
| Keywords: virtual memory TLB addressing translation pre-validated Cache address line tag |
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