| 引用本文: | 邹丹,窦勇,夏飞,等.基于FPGA的带回溯的Smith-Waterman算法加速器的设计与实现.[J].国防科技大学学报,2009,31(5):29-32.[点击复制] |
| ZOU Dan,DOU Yong,XIA Fei,et al.FPGA-based Smith-Waterman Algorithm Accelerator with Backtracking[J].Journal of National University of Defense Technology,2009,31(5):29-32[点击复制] |
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| 基于FPGA的带回溯的Smith-Waterman算法加速器的设计与实现 |
| 邹丹, 窦勇, 夏飞, 倪时策 |
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(国防科技大学 计算机学院，湖南 长沙 410073)
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| 摘要: |
| 针对传统的Smith-Waterman硬件算法加速器未保存回溯路径而无法回溯的问题，通过将计算路径存入外存，在FPGA平台上基于脉动阵列实现了带回溯的 Smith-Waterman算法加速器，详细阐述了算法加速器回溯设计中的关键技术以及算法加速器的系统结构。实验表明，与传统的解决方案相比，带回溯的算法加速器最高可获得161倍加速比，能够有效提高带回溯的Smith-Waterman算法执行效率。 |
| 关键词: FPGA Smith-Waterman算法 脉动阵列；回溯 |
| DOI： |
| 投稿日期：2009-07-03 |
| 基金项目:教育部“高性能微处理器技术”创新团队资助项目(IRT0614) |
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| FPGA-based Smith-Waterman Algorithm Accelerator with Backtracking |
| ZOU Dan, DOU Yong, XIA Fei, NI Shice |
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(College of Computer, National Univ. of Defense Technology， Changsha 410073，China)
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| Abstract: |
| The Smith-Waterman algorithm accelerator with backtracking, which has not been implemented in hardware before, is designed and implemented on FPGA platform with systolic array by storing the path data into DRAM. The key techniques of backtracking design and the architecture of algorithm accelerator are discussed in detail. Compared with the conventional scheme, the FPGA-based accelerator with backtracking is more effective, with the acceleration reaching 161. |
| Keywords: FPGA Smith-Waterman algorithm systolic array backtracking |
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