| 引用本文: | 石伟,王友瑞,陈芳园,等.低功耗微处理器中异步流水线设计.[J].国防科技大学学报,2009,31(5):33-37.[点击复制] |
| SHI Wei,WANG Yourui,CHEN Fangyuan,et al.Design of Asynchronous Pipelines for Low-power Microprocessor[J].Journal of National University of Defense Technology,2009,31(5):33-37[点击复制] |
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| 低功耗微处理器中异步流水线设计 |
| 石伟, 王友瑞, 陈芳园, 任洪广, 陆洪毅, 王志英 |
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(国防科技大学 计算机学院，湖南 长沙 410073)
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| 摘要: |
| 随着工艺的不断进步及芯片上资源的不断增加，微处理器设计遇到了一系列问题：为芯片提供一个全局时钟网络越来越困难，时钟扭曲等问题越来越突出，芯片的功耗问题越来越严重。上述这些因素促使人们将注意力逐渐转向异步电路设计。在设计异步微处理器过程中，异步流水线的设计是一个非常重要的问题。首先总结了微处理器设计中出现的各种流水线结构，并给出了相应的异步实现；然后提出了一种异步流水线设计流程，用于加速异步流水线的设计；最后利用提出的流程设计实现了几种异步功能单元，实验结果表明异步电路能够有效降低电路的功耗。 |
| 关键词: 低功耗 流水线 异步电路 设计流程 |
| DOI： |
| 投稿日期：2009-07-03 |
| 基金项目:国家863计划资助项目(2007AA01Z101)；国家自然科学基金资助项目(60873015，60773024)；国防科技大学校资助项目(JC-08-06-02)；教育部“高性能微处理器技 术”创新团队资助项目(IRT0614) |
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| Design of Asynchronous Pipelines for Low-power Microprocessor |
| SHI Wei, WANG Yourui, CHEN Fangyuan, REN Hongguang, LU Hongyi, WANG Zhiying |
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(College of Computer, National Univ. of Defense Technology， Changsha 410073，China)
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| Abstract: |
| As the CMOS technology enters the deep submicron design era, the richness of the computational resources brings about a lot of problems, such as clock distribution, clock skew and high power dissipation. Asynchronous circuit style is an efficient approach to solve the problems, and it is becoming significantly attractive to the designers. The design of asynchronous pipelines is a very important issue in the process of designing asynchronous microprocessors. In this paper, various pipeline structures are summarized and their asynchronous equivalents are presented, and then an asynchronous flow is proposed, aiming at speeding up the asynchronous circuit design. Finally, the flow is used to design several asynchronous pipelines. The experimental results show that the asynchronous technique can reduce the power consumption of microprocessor effectively. |
| Keywords: low-power pipeline asynchronous circuit design flow |
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