| 引用本文: | 周宏伟,邓让钰,窦强,等.一种多核微处理器互连接口的设计与性能分析.[J].国防科技大学学报,2010,32(4):94-99.[点击复制] |
| ZHOU Hongwei,DENG Rangyu,DOU Qiang,et al.Design and Performance Analysis of an Interconnect Interface for Multi-Core Microprocessor[J].Journal of National University of Defense Technology,2010,32(4):94-99[点击复制] |
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| 一种多核微处理器互连接口的设计与性能分析 |
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(1.国防科技大学 计算机学院，湖南 长沙 410073;2.中国舰船研究院，北京 100191)
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| 摘要: |
| 并行是提高计算机性能最主要的方法，随着集成电路生产工艺的不断发展，除了在单个芯片内集成更多的处理器核外，通过集成高速互连网络接口构建多路并行系统一直是提高高性能计算机并行性的主要方式。提出了一种面向多核微处理器的互连接口的设计方案，基于精简的PCI-E总线协议，采用高速串行数据传输技术，支持Cache一致性报文和大块数据传输报文，能够用于实现4个处理器的直接互连。模拟结果表明，优化设计的互连接口每个接口能够实现64Gbps的双向最大有效带宽，最小传输延迟为120ns，能够较好平衡不同报文类型对带宽和传输延时的要求。 |
| 关键词: 多核处理器 互连 PCI-E |
| DOI： |
| 投稿日期：2009-10-09 |
| 基金项目:国家“863”计划项目(2009AA01Z124) |
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| Design and Performance Analysis of an Interconnect Interface for Multi-Core Microprocessor |
| ZHOU Hongwei1,2, DENG Rangyu1, DOU Qiang1, QI Shubo1, SHEN Changyun3 |
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(1.College of Computer, National Univ. of Defense Technology, Changsha 410073, China;2. 2.China Ship Research & Development Academy, Beijing 100191, China;3.2.China Ship Research & Development Academy, Beijing 100191, China)
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| Abstract: |
| Parallelism is the most important way to improve the performance of computer. With the development of the integrated circuits' manufacture process, besides integrating more processor cores into one processor chip, building multi-way parallelism system through high-speed interconnect interface is the main method to increase the parallelism of high-performance computer. A design scheme of an interconnect interface for multi-core microprocessor was proposed. The proposed interface was based on a simplified PCI Express bus protocol and adopted the technology of high-speed serial data transferring. Cache coherence packet and large block data transfer packet were all supported. The interface can be used for connecting four processor nodes directly. Simulation results show that the max valid bandwidth per interface can reach 64Gbps and the minimum transfer delay is 120ns. The balance of the bandwidth and the transfer delay is reached, meeting the requirement of transferring different type of packets. |
| Keywords: multi-core processor interconnect PCI-E |
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