| 引用本文: | 秦军瑞,陈书明,陈建军,等.180nm CMOS工艺下SEL敏感性关键影响因素.[J].国防科技大学学报,2011,33(3):72-76.[点击复制] |
| QIN Junrui,CHEN Shuming,CHEN Jianjun,et al.Key Factors of Single Event Latch-up in 180nm CMOS Technologies[J].Journal of National University of Defense Technology,2011,33(3):72-76[点击复制] |
|
| |
|
|
| 本文已被：浏览 8223次 下载 6182次 |
| 180nm CMOS工艺下SEL敏感性关键影响因素 |
| 秦军瑞, 陈书明, 陈建军, 梁斌, 刘必慰 |
|
(国防科技大学 计算机学院，湖南 长沙 410073)
|
| 摘要: |
| 研究了影响SEL敏感性的关键因素。针对180nm体硅工艺，基于校准的CMOS反相器器件模型，使用器件模拟的方法，研究了粒子入射位置、温度、阱/衬底接触位置、NMOS与PMOS间距等因素对SEL敏感性的影响。模拟和分析表明，CMOS电路不同位置的闩锁响应差别很大，找出了电路发生闩锁的敏感区域，得出了温度、阱/衬底接触的位置、NMOS与PMOS间距等因素与SEL敏感性之间的关系，并从理论上进行了解释，总结了降低单粒子闩锁效应的有效方法，研究结果能为深亚微米体硅工艺下的抗SEL加固设计提供有效的指导。 |
| 关键词: 单粒子闩锁 器件模拟 设计加固 |
| DOI： |
| 投稿日期：2010-11-01 |
| 基金项目:国家自然科学基金资助项目(60836004，61006070)；高等学校博士点基金资助项目(20104307120006) |
|
| Key Factors of Single Event Latch-up in 180nm CMOS Technologies |
| QIN Junrui, CHEN Shuming, CHEN Jianjun, LIANG Bin, LIU Biwei |
|
(College of Computer, National Univ. of Defense Technology, Changsha 410073, China)
|
| Abstract: |
| The key factors that affect Single Event Latch-up sensitivity were investigated. In view of 180nm bulk technology, based on calibrated CMOS inverter model, TCAD method was adopted to study the effects of particle incident position, temperature, and well / substrate contact position, NMOS and PMOS spacing and other factors on SEL sensitivity. Simulation and analysis shows that, SEL response varies greatly at different nodes, and the study identified the sensitive nodes of the CMOS inverter of SEL occurrence, and explored the relationship between temperature, well / substrate contact position, NMOS and PMOS drain distance and LET threshold when SEL occurred, then analyzed theoretically and summarized the reinforcement for reducing SEL sensitivity. The results can provide effective guidance to the anti-SEL design. |
| Keywords: single event latch-up TCAD reinforcement by design |
|
|
|
|
|
