| 引用本文: | 周宏伟,陈超,张丽霞,等.板级高速传输总线链路层关键技术研究与实现.[J].国防科技大学学报,2011,33(6):55-60.[点击复制] |
| ZHOU Hongwei,CHEN Chao,ZHANG Lixia,et al.Research and Design of Link Layer in Board-level High-speed Transportation Bus[J].Journal of National University of Defense Technology,2011,33(6):55-60[点击复制] |
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| 板级高速传输总线链路层关键技术研究与实现 |
| 周宏伟1, 陈超1, 张丽霞2, 张英1, 李永进1 |
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(1.国防科技大学 计算机学院，湖南 长沙 410073;2.湖南师范大学 数学与计算机学院，湖南 长沙 410081)
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| 摘要: |
| 随着高性能服务器和超大规模计算机的发展，系统设计者对板上高速互连总线的要求越来越高，如何使芯片间的数据传输延迟更小，提高计算通信比是需要解决的重要问题。论文研究了近年来发展迅速的超传输总线和PCI Express总线的链路层的特点，在此基础上提出了一种64位高速总线链路层体系结构，并对其关键技术进行了研究，设计实现了一种能够每时钟周期对16位数据进行加解扰的加解扰器，以及能够纠正链路间最大5个时钟周期延迟偏斜的线间传输延迟偏斜纠正器，功能验证结果表明所提出的设计功能正确。 |
| 关键词: 板级 传输总线 链路层 加解扰 延迟偏斜纠正 |
| DOI： |
| 投稿日期：2011-06-20 |
| 基金项目:国家自然科学基金资助项目（61003075）；湖南师范大学青年基金资助项目（数100636）；国家“核高基”重大专项“超高性能CPU新型架构研究”资助项目（2011ZX01028-001-001） |
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| Research and Design of Link Layer in Board-level High-speed Transportation Bus |
| ZHOU Hongwei1, CHEN Chao1, ZHANG Lixia2, ZHANG Ying1, LI YongJin1 |
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(1.College of Computer, National Univ. of Defense Technology, Changsha 410073, China;2.College of Mathematics and Computer, Hunan Normal Univ, Changsha 410081, China)
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| Abstract: |
| With the development of the high performance servers and very large scale super computers, the requirement for board-level high-speed data transportation bus is higher than before. How to reduce the transfer delay between chips and improve the ratio of computation to communication is very important. In light of this, the characteristics of link layer in Hyper Transport and PCI Express buses which are very popular in recent years was studied. On the basis of this, link layer architecture for a 64-bit high-speed data transportation bus was proposed and some key technologies were researched. A 16-bit scrambler/descrambler, which can scramble or descramble a 16-bit data in one cycle, was designed. A lane-to-lane deskew logic, which can correct 5 cycles delay skews at most between two lanes, was also proposed. The verification results show that the function of our designs is correct. |
| Keywords: board-level data transportation bus link layer scrambler/descrambler lane-to-lane deskew |
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