| 引用本文: | 李振涛,刘尧,陈书明,等.YHFT-DX处理器全定制EDA技术的开发与应用.[J].国防科技大学学报,2013,35(1):151-154.[点击复制] |
| LI Zhentao,LIU Yao,CHEN Shuming,et al.The development and application of full custom EDA techniques in YHFT-DX[J].Journal of National University of Defense Technology,2013,35(1):151-154[点击复制] |
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| YHFT-DX处理器全定制EDA技术的开发与应用 |
| 李振涛, 刘尧, 陈书明, 徐庆光, 付志刚 |
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(国防科技大学 计算机学院，湖南 长沙 410073)
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| 摘要: |
| 在YHFT-DX处理器的研制中，研究并实现了多项支撑全定制设计的EDA技术。针对全定制设计的功能验证，研究并实现了层次式功能模型自动提取技术，能够将晶体管级网表转化为等效的RTL级网表。研究并实现了晶体管级混合时序分析方法，可自动分析全定制设计的延时，并采用多线程并行的方法获得了约10倍左右的速度提升。为提高模拟结果分析的效率，开发了一个延时提取的工具Aimeasure。开发了两个信号完整性分析工具PNVisual和NoiseSpy，分别用于全定制设计的IR-Drop分析和噪声分析。上述技术已在YHFT-DX处理器的设计中得到了广泛应用，有效提高了全定制设计的效率与质量。 |
| 关键词: 全定制设计 功能验证 时序分析 IR-Drop 噪声分析 |
| DOI： |
| 投稿日期：2012-05-13 |
| 基金项目:国家自然科学基金重点资助项目（60906014） |
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| The development and application of full custom EDA techniques in YHFT-DX |
| LI Zhentao, LIU Yao, CHEN Shuming, XU Qingguang, FU Zhigang |
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(College of Computer, National University of Defense Technology,
Changsha 410073, China)
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| Abstract: |
| Several full custom EDA techniques were developed during the design of YHFT-DX processor. Hierarchical functional model extraction, which can convert a transistor-level netlist into an equivalent RTL netlist, were developed for the functional verification of full custom circuits. Hybrid timing analysis was researched for the transistor-level timing analysis. 10x run-time improvements were achieved by the multi-thread parallel optimization. A measurement was developed to get delays from the simulation waveforms, which improves the efficiency of simulation results analysis. Two signal integrity verification tools, PNVisual and NoiseSpy, were developed for IR-Drop and noise analysis of full custom circuits. These techniques have been widely used in the design of YHFT-DX, which greatly improves the efficiency and quality of full custom design. |
| Keywords: full custom design functional verification timing analysis IR-Drop noise analysis |
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