| 引用本文: | 翟海涛,郄志鹏,张尔扬.可变速率调制器研究及其FPGA实现.[J].国防科技大学学报,2014,36(2):124-128.[点击复制] |
| ZHAI Haitao,XI Zhipeng,ZHANG Eryang.Research on variable rate modulator and its implementation on FPGA[J].Journal of National University of Defense Technology,2014,36(2):124-128[点击复制] |
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| 可变速率调制器研究及其FPGA实现 |
| 翟海涛, 郄志鹏, 张尔扬 |
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(国防科技大学 电子科学与工程学院， 湖南 长沙 410073)
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| 摘要: |
| 提出了一种变速率调制系统的设计方法。基于现场可编程门阵列（FPGA），在硬件系统中实现了新方法。所设计的系统能够处理(13.5～300)Mbps连续变化的比特速率。通过将整个可变速率范围分成若干小段，分别经过不同倍数的采样滤波，保证了所有符号速率对应的数据能够被调制到数模转换芯片（DAC）处理范围内。给出了系统整体设计结构，分析了硬件实现时的难点，论述了并行采样滤波与并行载波生成等设计方法。硬件实现结果表明，所提出的设计方法能够实现对较宽范围内连续可变速率信号的调制。系统的易扩展性也保证了所设计结构能够处理更宽的变速率范围。 |
| 关键词: 变速率；调制器；比特速率；并行滤波 现场可编程门阵列；数模转换芯片 |
| DOI：10.11887/j.cn.201402021 |
| 投稿日期：2013-08-06 |
| 基金项目:国家863计划资助项目；青年科学基金项目（61201166） |
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| Research on variable rate modulator and its implementation on FPGA |
| ZHAI Haitao, XI Zhipeng, ZHANG Eryang |
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(College of Electronic Science and Engineering, National University of Defense Technology, Changsha 410073, China)
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| Abstract: |
| A variable modulator scheme is presented. The hardware system adopting the proposed approach was accomplished based on field programmable gate array (FPGA). The proposed system can deal with signals with bit rate even varying from （13.5～300）Mbps continuously. By splitting the whole rate range into several small parts and filtering the input data with different interpolation times, the correctness of transferring all rates into the dealing range of digital analog convert (DAC) was ensured. The architecture of system was devised and the difficulties in hardware realization were analysed. The ways to solve the pivotal problem were particularly indicated. Realization on FPGA demonstrates the good performance of the proposed idea. The expansibility of system makes it easy to be applied in wider rate bound. |
| Keywords: variable rate modulator bit rate parallel filtering FPGA DAC |
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