| 引用本文: | 江金光,唐亚男,周细凤,等.0.18 μm CMOS工艺的GPS/BDS双模可重构接收机射频前端.[J].国防科技大学学报,2016,38(3):19-24.[点击复制] |
| JIANG Jinguang,TANG Yanan,ZHOU Xifeng,et al.A dual-mode reconfigurable GPS/BDS radio frequency front-end receiver in 0.18 μm CMOS process[J].Journal of National University of Defense Technology,2016,38(3):19-24[点击复制] |
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| 0.18 μm CMOS工艺的GPS/BDS双模可重构接收机射频前端 |
| 江金光1, 唐亚男1, 周细凤2, 刘江华2 |
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(1.武汉大学 卫星导航定位技术研究中心， 湖北 武汉 430079;2.武汉大学 物理科学与技术学院， 湖北 武汉 430072)
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| 摘要: |
| 采用低中频架构设计了一种0.18μm CMOS工艺的GPS/BDS双模可重构接收机射频前端，能在GPS L1模式或BDS B1模式下工作。通过频率自适应电路调整中频滤波器的时间常数,降低其频率不确定度；压控振荡器中加入4位开关电容阵列，以提高频率调谐范围和相位噪声性能；通过硬件复用的方式降低系统功耗。测试结果表明，在1.8 V电源电压下，功耗37.8 mW，电压增益为103 dB，GPS L1和BDS B1波段噪声系数均小于3.2 dB。 |
| 关键词: 可重构 低中频架构 射频前端 双模 GPS/BDS |
| DOI：10.11887/j.cn.201603004 |
| 投稿日期：2016-02-07 |
| 基金项目:国家自然科学基金资助项目(41274047)；广东省科技计划资助项目(2013B090500049) |
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| A dual-mode reconfigurable GPS/BDS radio frequency front-end receiver in 0.18 μm CMOS process |
| JIANG Jinguang1, TANG Yanan1, ZHOU Xifeng2, LIU Jianghua2 |
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(1. GNSS Research Center, Wuhan University, Wuhan 430079, China;2. School of Physics and Technology, Wuhan University, Wuhan 430072, China)
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| Abstract: |
| A dual-mode reconfigurable GPS L1/BDS B1 radio frequency front-end adopting low intermediate frequency architecture was realized in 0.18μm CMOS process. An auto-calibrating circuit was used to adjust the intermediate frequency filter′s time constant and to reduce frequency uncertainty. A 4-bits capacitors array was designed to widen the frequency tuning range of the voltage controlled oscillator and to improve phase noise performance. The system power consumption was reduced by hardware reuse technique. Test results show that the power consumption is 37.8mW with 1.8V voltage supply, and the voltage gain is 103dB, while the noise figures are less than 3.2dB in both GPS L1 and BDS B1. |
| Keywords: reconfigurable low intermediate frequency architecture radio frequency front-end dual-mode GPS/BDS |
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