| 引用本文: | 李鹏,郭维,赵振宇,等.65 nm工艺双层三维静态存储器的软错误分析与评估.[J].国防科技大学学报,2016,38(5):20-25.[点击复制] |
| LI Peng,GUO Wei,ZHAO Zhenyu,et al.Soft error analysis and evaluation of dual-layer 3D SRAM based on 65 nm technology[J].Journal of National University of Defense Technology,2016,38(5):20-25[点击复制] |
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| 65 nm工艺双层三维静态存储器的软错误分析与评估 |
| 李鹏1, 郭维1, 赵振宇1, 张民选1,2, 邓全1, 周宏伟1 |
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(1.国防科技大学 计算机学院， 湖南 长沙 410073;2.
2.国防科技大学 并行与分布处理国家重点实验室， 湖南 长沙 410073)
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| 摘要: |
| 新兴的三维静态存储器将代替二维静态存储器被广泛用于高性能微处理器中，但它依然会受到软错误的危害。为了能够快速、自动分析多层管芯堆叠结构的三维静态存储器软错误特性，搭建了三维静态存储器软错误分析平台。利用该平台对以字线划分设计的三维静态存储器和同等规模的二维静态存储器分别进行软错误分析，并对分析结果进行对比。研究结果表明二维和三维静态存储器的翻转截面几乎相同，但三维静态存储器单个字中发生的软错误要比二维静态存储器更严重，导致难以使用纠检错技术对其进行加固。静态模式下二维和三维静态存储器敏感节点均分布于存储阵列中，表明静态模式下逻辑电路不会引发软错误。 |
| 关键词: 三维静态存储器 软错误 分析平台 翻转截面 单粒子翻转 多位翻转 |
| DOI：10.11887/j.cn.201605004 |
| 投稿日期：2015-11-11 |
| 基金项目:国家自然科学基金资助项目（61373032，61303069）；高等学校博士学科点专项科研基金资助项目（20124307110016） |
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| Soft error analysis and evaluation of dual-layer 3D SRAM based on 65 nm technology |
| LI Peng1, GUO Wei1, ZHAO Zhenyu1, ZHANG Minxuan1,2, DENG Quan1, ZHOU Hongwei1 |
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(1.College of Computer, National University of Defense Technology, Changsha 410073, China;2.
2. National Key Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, China)
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| Abstract: |
| The 3D SRAM (three-dimensional static random access memory) will take the place of 2D SRAM (two-dimensional static random access memory), and will be widely used in high performance microprocessor. However, 3D SRAM still suffers from the dangers of soft error. A novel 3D SRAM soft error analysis platform was designed for studying the soft error characteristic of 3D SRAM. The soft error characteristic of the designed 3D SRAM and the original 2D SRAM were analyzed by using our designed platform. It is found that 3D SRAM and 2D SRAM have the same upset cross section, but the soft error of 3D SRAM is more serious than that of 2D SRAM, which makes it difficult to harden 3D SRAM by using error correction codes technologies. At the static test mode, the upset sensitive nodes were only distributed in the memory array of both 3D SRAM and 2D SRAM. It indicates that the logic circuit can’t induce soft error at static test mode. |
| Keywords: three-dimensional static random access memory soft error analysis platform cross section single event upset multi cell upset |
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