引用本文: | 徐金波,庞征斌,李琰.位置信息与替换概率相结合的多核共享Cache管理机制[J].国防科技大学学报,2016,38(5):32-38.[点击复制] |
XU Jinbo,PANG Zhengbin,LI Yan.Shared Cache management scheme with location information and eviction probability in multi-core system[J].Journal of National University of Defense Technology,2016,38(5):32-38[点击复制] |
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位置信息与替换概率相结合的多核共享Cache管理机制 |
徐金波1, 庞征斌1,2, 李琰1 |
(1.国防科技大学 计算机学院, 湖南 长沙 410073;2.2.国防科技大学 并行与分布式计算重点实验室, 湖南 长沙 410073)
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摘要: |
多核系统中末级Cache是影响整体性能的关键。为了提出一种细粒度、低延迟、低代价的末级共享Cache资源管理机制,将系统性能目标转换为每个内核当前占用Cache资源的替换概率,以决定每个内核能够提供的被替换资源的数量;对某个需要增加Cache资源的内核,从可提供被替换资源的候选内核中选出距离较近且替换概率较高的一个内核,并以Cache块为粒度进行替换,从而实现Cache资源在不同内核间的动态划分。与传统以相联度为粒度的粗粒度替换机制相比,以Cache块为单位的替换机制具有更细的替换粒度,灵活性更高。另外,通过将位置信息和替换概率结合,保证了Cache资源与相应内核在物理布局上的收敛,降低了访问延迟。同时,所提出的方法只需要增加极少的硬件代价。实验结果表明,根据实验场景和对比对象的不同,所提方法与其他已有研究成果相比,可以实现从6.8%到22.7%的性能提升。 |
关键词: 多核系统 末级Cache 动态划分 替换策略 |
DOI:10.11887/j.cn.201605006 |
投稿日期:2015-11-19 |
基金项目:国家自然科学基金资助项目(61202126);国家863计划资助项目(2012AA01A301,2013AA01A208);国家部委基金资助项目(2011CB309705-1) |
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Shared Cache management scheme with location information and eviction probability in multi-core system |
XU Jinbo1, PANG Zhengbin1,2, LI Yan1 |
(1. College of Computer, National University of Defense Technology, Changsha 410073, China;2.
2. Science and Technology on Parallel and Distributed Processing Laboratory, National University of Defense Technology, Changsha 410073, China)
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Abstract: |
LLC (last level Cache) plays an important role in multi-core systems. A shared LLC management scheme with fine granularity, low latency and simple hardware complexity was proposed. The performance goal was translated into eviction probabilities of each core. Then, a victim core, which was near the current core and had higher eviction probability was chosen to provide the victim block for replacement. In this way, LLC was dynamically partitioned among all cores at finer granularity of Cache blocks. This proposal is more flexible than traditional way-partitioning scheme. In addition, the combination of location information and eviction probability improves the locality between Cache resources and the corresponding cores, which can reduce the Cache access latency. The proposed scheme requires only little additional hardware changes to traditional Cache structure. Results on M5 simulator suggest that the performance can improve from 6.8% to 22.7% when comparing with the related works. |
Keywords: multi-core system last-level Cache dynamic partitioning replacement policy |
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