| 引用本文: | 姚睿,何坤,朱萍,等.使用位流重定位与差异配置在线演化数字系统.[J].国防科技大学学报,2017,39(3):69-76.[点击复制] |
| YAO Rui,HE Kun,ZHU Ping,et al.Online evolution of the digital system on bitstream relocation and discrepancy configuration[J].Journal of National University of Defense Technology,2017,39(3):69-76[点击复制] |
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| 使用位流重定位与差异配置在线演化数字系统 |
| 姚睿, 何坤, 朱萍, 李增武, 羊宇中 |
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(南京航空航天大学 自动化学院， 江苏 南京 210016)
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| 摘要: |
| 利用位流重定位与差异配置技术对现有基于动态部分重构的演化硬件实现方法进行改进，以解决其演化复杂电路时位流存储开销大和演化速度慢的问题。利用Xilinx早期获取部分重构技术，定制能实现位流重定位的可演化IP核。原始位流文件经设计形成算子核位流库存于外部CF卡上，方便系统调用。将现场可编程门阵列片内软核处理器MicroBlaze作为演化控制器，采用染色体差异配置技术，在线实时调节可演化IP核的电路结构，构成基于片上可编程系统的自演化系统。以图像滤波器的在线演化设计为例，在Virtex-5 现场可编程门阵列开发板ML507上对系统结构和演化机制进行验证，结果表明，所提演化机制能有效节省位流存储空间，提高演化速度。 |
| 关键词: 演化硬件 现场可编程门阵列 位流重定位 差异配置 自演化 |
| DOI：10.11887/j.cn.201703012 |
| 投稿日期：2016-01-12 |
| 基金项目:国家自然科学基金资助项目（61402226）；中央高校基本科研业务费专项资金资助项目（ NS2014036） |
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| Online evolution of the digital system on bitstream relocation and discrepancy configuration |
| YAO Rui, HE Kun, ZHU Ping, LI Zengwu, YANG Yuzhong |
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(College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China)
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| Abstract: |
| To break through the limitations of huge memory space and low evolution speed for complex circuits′ evolution, the bitstream relocation and the discrepancy configuration were adopted to improve the efficiency of the evolvable hardware implementation approach based on dynamic partial reconfiguration. Firstly, an evolvable IP core capable of bitstream relocation was customized by using the technology of early stage accession to partial reconfiguration provided by Xilinx. Then the original bitstream files were pre synthesized to form a partial bitstreams library stored in the CF memory for the system to call. Next, a self-evolving system based on a programmable chip system was built, in which the soft processor, MicroBlaze, was utilized as the evolution controller. And the discrepancy configuration was adopted for the real-time adjustment of the circuit topology of the evolvable IP core. Finally, the system structure and the self-evolving mechanisms were verified by the online evolution of digital image filters implemented on the Xilinx Virtex-5 FPGA(field programmable gate array) development board ML507. Experimental results show that the proposed evolutionary mechanisms can reduce the storage space of bitstream files and can accelerate the speed of evolution significantly. |
| Keywords: evolvable hardware field programmable gate array bitstream relocation discrepancy configuration self-evolution |
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